The Taiwanese chipmaker intends to increase the capacity of its co-packaged optics (CPO) by 128 fold to handle the data load of artificial intelligence clusters. This scaling plan relies on boosting single channel speeds from 200G to 400G and increasing optical channel counts from 16 to 64. TSMC proposes a new scaling cadence for optics, similar to Moore's Law, to overcome the power and reach limitations of copper wiring inside data center racks.
A media report forecasts that this pace will drive CPO bandwidth from a current 3.2T baseline to roughly 410T by 2040. The strategy incorporates wavelength division multiplexing to allow single optical fibers to carry multiple simultaneous wavelengths. TSMC is integrating CPO into its CoWoS and 3DFabric packaging along with the COUPE silicon photonics engine to place compute and high bandwidth memory in one package, provided packaging yield and thermal control can keep pace.
Key sources
- SOURCE@dnystedt“TSMC could create a new “Moore’s Law for CPO,” doubling bandwidth every two years as it accelerates the rollout of co-packaged optics (CPO) to meet the soaring bandwidth requirements of AI data centers”x.com
- SUPPORT@semiconductorsx“folding CPO into CoWoS, 3DFabric and the COUPE silicon-photonics engine so compute, HBM and optical I/O sit in one package”x.com
- SUPPORT@egarciagarcia“TSMC is floating a Moore’s Law for co-packaged optic ➡️Double optical bandwidth every two years as copper runs out of power and reach”x.com
- SOURCEmarketbrief.now