--- format: "aidr-story-markdown/v1" id: "e4870357d33045a4a11503c32edd7724c3f50b4b2b975532a0f110dec5dda218" canonical_url: "https://aidr.today/e4870357?lang=en" title: "TSMC Plans 2 Year Optical Bandwidth Double to Reach 410T by 2040" lang: "en" requested_lang: "en" available_langs: ["en","vi"] translation_fallback: null fallback_fields: [] published_at: "2026-09-14T08:58:31.000Z" category: "Chips" topics: ["tsmc","chips","infra","optical-bandwidth"] source_urls: ["https://huggingnews.com/tech/tsmc-plans-2-year-optical-bandwidth-double-to-reach-410t-by-2040-b1effa92","https://x.com/dnystedt/status/2099313721890017676","https://x.com/SemiconductorsX/status/2099345966906392802","https://x.com/egarciagarcia/status/2099357960229065159","https://marketbrief.now/tech/tsmc-plans-2-year-optical-bandwidth-double-to-reach-410t-by-2040-b1effa92"] summary: "The Taiwanese chipmaker intends to increase the capacity of its co-packaged optics (CPO) by 128 fold to handle the data load of artificial intelligence clusters. This scaling plan relies on boosting single channel speeds from 200G to 400G and increasing optical channel counts from 16 to 64. TSMC proposes a new scaling cadence for optics, similar to Moore's Law, to overcome the power and reach limitations of copper wiring inside data center racks. A media report forecasts that this pace will drive CPO bandwidth from a current 3.2T baseline to roughly 410T by 2040. The strategy incorporates wavelength division multiplexing to allow single optical fibers to carry multiple simultaneous wavelengths. TSMC is integrating CPO into its CoWoS and 3DFabric packaging along with the COUPE silicon photonics engine to place compute and high bandwidth memory in one package, provided packaging yield and thermal control can keep pace." --- # TSMC Plans 2 Year Optical Bandwidth Double to Reach 410T by 2040 > [Open the canonical story]() **Published:** 2026-09-14T08:58:31.000Z **Category:** Chips **Topics:** tsmc, chips, infra, optical\-bandwidth ## Summary The Taiwanese chipmaker intends to increase the capacity of its co\-packaged optics \(CPO\) by 128 fold to handle the data load of artificial intelligence clusters\. This scaling plan relies on boosting single channel speeds from 200G to 400G and increasing optical channel counts from 16 to 64\. TSMC proposes a new scaling cadence for optics, similar to Moore's Law, to overcome the power and reach limitations of copper wiring inside data center racks\. A media report forecasts that this pace will drive CPO bandwidth from a current 3\.2T baseline to roughly 410T by 2040\. The strategy incorporates wavelength division multiplexing to allow single optical fibers to carry multiple simultaneous wavelengths\. TSMC is integrating CPO into its CoWoS and 3DFabric packaging along with the COUPE silicon photonics engine to place compute and high bandwidth memory in one package, provided packaging yield and thermal control can keep pace\. ## Sources - [Story source]() - [Story source]() - [Supporting source]() - [Supporting source]() - [Story source]()