TSMC, Samsung, Intel, and ASML are collaborating to implement 12 inch photomasks for High NA EUV lithography to eliminate a 30% throughput loss caused by reticle stitching. The current 6 inch masks halve the exposure field, forcing large AI accelerator dies to be printed across two exposures. The new 12 inch standard enables single shot printing for large chips on scanners that cost $380 million to $400 million per unit.
TSMC will start high volume production using High NA EUV in 2030, focusing on advanced nodes to scale beyond the 1 nanometer class. The company plans to use conventional 6 inch masks initially before transitioning to 12 inch masks by 2033. An industry pilot line for the larger mask format is targeted for 2031 to reduce per chip capital costs for next generation AI accelerators.
Key sources
- SOURCE@asmlcompany“rallying the chip industry around larger masks to give High NA EUV a productivity boost”x.com
- SUPPORT@photoncap“A10 or A11 (1/1.1nm-class) process nodes are prime candidates for initial High-NA EUV adoption”x.com
- SUPPORT@photoncap“12-inch masks restore full 26 mm × 33 mm exposure field”x.com
- SUPPORT@tculpan“This is HUGE news for @ASMLcompany”x.com
- SOURCE@reuters“work with major chipmakers to use latest tools for larger chips”x.com
- SUPPORT@cnbc“TSMC, Samsung commit to ASML’s newest chipmaking tools as AI drives demand”x.com
- SUPPORT@wallstengine“targets a 12-inch mask pilot line by 2031 and advanced-node production using 12-inch High NA EUV by 2033”x.com
- SUPPORT@wallstengine“High-NA EUV in future high-volume DRAM manufacturing by 2028, which the companies say would be an industry first”x.com