---
format: "aidr-story-markdown/v1"
id: "4c87fd5f237b38537d256d37bb7b5a0db3c4d33f4360e5c78146b86879914e91"
canonical_url: "https://aidr.today/4c87fd5f?lang=en"
title: "ASML and TSMC Adopt 12 Inch EUV Masks to End 30% Throughput Loss"
lang: "en"
requested_lang: "en"
available_langs: ["en","vi"]
translation_fallback: null
fallback_fields: []
published_at: "2026-09-08T18:43:38.000Z"
category: "Chips"
topics: ["nvidia","chips","infra"]
source_urls: ["https://huggingnews.com/tech/asml-and-tsmc-adopt-12-inch-euv-masks-to-end-30percent-throughput-loss-f8acdeb4","https://x.com/ASMLcompany/status/2097210093687185825","https://x.com/PhotonCap/status/2097360980682711049","https://x.com/PhotonCap/status/2097361677159366871","https://x.com/tculpan/status/2097226305247076608","https://x.com/Reuters/status/2097215886536937613","https://x.com/CNBC/status/2097244314233401452","https://x.com/wallstengine/status/2097268421654360290"]
summary: "TSMC, Samsung, Intel, and ASML are collaborating to implement 12 inch photomasks for High NA EUV lithography to eliminate a 30% throughput loss caused by reticle stitching. The current 6 inch masks halve the exposure field, forcing large AI accelerator dies to be printed across two exposures. The new 12 inch standard enables single shot printing for large chips on scanners that cost $380 million to $400 million per unit. TSMC will start high volume production using High NA EUV in 2030, focusing on advanced nodes to scale beyond the 1 nanometer class. The company plans to use conventional 6 inch masks initially before transitioning to 12 inch masks by 2033. An industry pilot line for the larger mask format is targeted for 2031 to reduce per chip capital costs for next generation AI accelerators."
---

# ASML and TSMC Adopt 12 Inch EUV Masks to End 30% Throughput Loss

> [Open the canonical story](<https://aidr.today/4c87fd5f?lang=en>)

**Published:** 2026-09-08T18:43:38.000Z
**Category:** Chips
**Topics:** nvidia, chips, infra

## Summary

TSMC, Samsung, Intel, and ASML are collaborating to implement 12 inch photomasks for High NA EUV lithography to eliminate a 30% throughput loss caused by reticle stitching\. The current 6 inch masks halve the exposure field, forcing large AI accelerator dies to be printed across two exposures\. The new 12 inch standard enables single shot printing for large chips on scanners that cost $380 million to $400 million per unit\. TSMC will start high volume production using High NA EUV in 2030, focusing on advanced nodes to scale beyond the 1 nanometer class\. The company plans to use conventional 6 inch masks initially before transitioning to 12 inch masks by 2033\. An industry pilot line for the larger mask format is targeted for 2031 to reduce per chip capital costs for next generation AI accelerators\.

## Sources

- [Story source](<https://huggingnews.com/tech/asml-and-tsmc-adopt-12-inch-euv-masks-to-end-30percent-throughput-loss-f8acdeb4>)
- [Story source](<https://x.com/ASMLcompany/status/2097210093687185825>)
- [Supporting source](<https://x.com/PhotonCap/status/2097360980682711049>)
- [Supporting source](<https://x.com/PhotonCap/status/2097361677159366871>)
- [Supporting source](<https://x.com/tculpan/status/2097226305247076608>)
- [Story source](<https://x.com/Reuters/status/2097215886536937613>)
- [Supporting source](<https://x.com/CNBC/status/2097244314233401452>)
- [Supporting source](<https://x.com/wallstengine/status/2097268421654360290>)