---
format: "aidr-story-markdown/v1"
id: "cb91a6f21f7868589f96f8350627623d5b192473a4c50f0e36ef5fa524081fde"
canonical_url: "https://aidr.today/cb91a6f2?lang=en"
title: "Meet qwenGPU: Qwen3.5-2B With 45 Compiled GPU Layers That Run CUDA"
lang: "en"
requested_lang: "en"
available_langs: ["en","vi"]
translation_fallback: null
fallback_fields: []
published_at: "2026-11-02T07:28:29.000Z"
category: "Models"
topics: ["llm"]
source_urls: ["https://www.marktechpost.com/2026/11/01/qwengpu-simt-gpu-compiled-into-qwen3-5-2b-weights-runs-cuda/"]
summary: "qwenGPU compiles a 4-lane SIMT GPU into Qwen3.5-2B as 45 untrained layers. The model writes every step of real CUDA launches itself, using Gated DeltaNet state as registers and memory."
---

# Meet qwenGPU: Qwen3\.5\-2B With 45 Compiled GPU Layers That Run CUDA

> [Open the canonical story](<https://aidr.today/cb91a6f2?lang=en>)

**Published:** 2026-11-02T07:28:29.000Z
**Category:** Models
**Topics:** llm

## Summary

qwenGPU compiles a 4\-lane SIMT GPU into Qwen3\.5\-2B as 45 untrained layers\. The model writes every step of real CUDA launches itself, using Gated DeltaNet state as registers and memory\.

## Sources

- [Story source](<https://www.marktechpost.com/2026/11/01/qwengpu-simt-gpu-compiled-into-qwen3-5-2b-weights-runs-cuda/>)