---
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id: "8d2eb8410437c5ccb77af9bbb65b91034205e6797b0a54cc7a0798d9f86108ad"
canonical_url: "https://aidr.today/8d2eb841?lang=en"
title: "Huawei Ships First LogicFolding Chip in Kirin 9050 Pro to Boost Density 55%"
lang: "en"
requested_lang: "en"
available_langs: ["en","vi"]
translation_fallback: null
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published_at: "2026-09-08T05:41:12.000Z"
category: "Chips"
topics: ["chips","infra","huawei"]
source_urls: ["https://huggingnews.com/tech/huawei-ships-first-logicfolding-chip-in-kirin-9050-pro-to-boost-density-80eeb199","https://x.com/ZhihuFrontier/status/2097159285037998272","https://x.com/UniverseIce/status/2097175579602862180","https://x.com/Reuters/status/2096980560283680955","https://x.com/teortaxesTex/status/2096947417920745895","https://x.com/ReutersBiz/status/2096980560245866654"]
summary: "The Mate XT 2 smartphone utilizes a 3D-stacked architecture that replaces long horizontal wires with short inter-layer links to reduce energy loss. This LogicFolding technology, part of the Tau Scaling Law, reduced clock buffers in one processing module from 43,600 to 19,000, a 56% reduction. The resulting Kirin 9050 Pro chipset enables a 42% overall performance increase for the device when paired with HarmonyOS 7, incorporating a Maleoon GPU with doubled cache and a Da Vinci NPU supporting the Pangu 30B-A2B MoE model. Vertical circuit folding reduces the need for traditional process-node scaling by shrinking signal distance rather than transistor size. Published results for the architecture showed a 55% increase in transistor density and power drops of 66%, 58%, and 41% for the NPU, GPU, and CPU respectively at matched performance. Implementing the design requires specialized Electronic Design Automation tools to optimize 3D routing and thermal hotspots to avoid power crises in stacked logic."
---

# Huawei Ships First LogicFolding Chip in Kirin 9050 Pro to Boost Density 55%

> [Open the canonical story](<https://aidr.today/8d2eb841?lang=en>)

**Published:** 2026-09-08T05:41:12.000Z
**Category:** Chips
**Topics:** chips, infra, huawei

## Summary

The Mate XT 2 smartphone utilizes a 3D\-stacked architecture that replaces long horizontal wires with short inter\-layer links to reduce energy loss\. This LogicFolding technology, part of the Tau Scaling Law, reduced clock buffers in one processing module from 43,600 to 19,000, a 56% reduction\. The resulting Kirin 9050 Pro chipset enables a 42% overall performance increase for the device when paired with HarmonyOS 7, incorporating a Maleoon GPU with doubled cache and a Da Vinci NPU supporting the Pangu 30B\-A2B MoE model\. Vertical circuit folding reduces the need for traditional process\-node scaling by shrinking signal distance rather than transistor size\. Published results for the architecture showed a 55% increase in transistor density and power drops of 66%, 58%, and 41% for the NPU, GPU, and CPU respectively at matched performance\. Implementing the design requires specialized Electronic Design Automation tools to optimize 3D routing and thermal hotspots to avoid power crises in stacked logic\.

## Sources

- [Story source](<https://huggingnews.com/tech/huawei-ships-first-logicfolding-chip-in-kirin-9050-pro-to-boost-density-80eeb199>)
- [Story source](<https://x.com/ZhihuFrontier/status/2097159285037998272>)
- [Supporting source](<https://x.com/UniverseIce/status/2097175579602862180>)
- [Story source](<https://x.com/Reuters/status/2096980560283680955>)
- [Supporting source](<https://x.com/teortaxesTex/status/2096947417920745895>)
- [Supporting source](<https://x.com/ReutersBiz/status/2096980560245866654>)