---
format: "aidr-story-markdown/v1"
id: "871d193932e074981dd0de78158d4366d0b62a01255f159ad38a0e9d8c4552ed"
canonical_url: "https://aidr.today/871d1939?lang=en"
title: "Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5"
lang: "en"
requested_lang: "en"
available_langs: ["en","vi"]
translation_fallback: null
fallback_fields: []
published_at: "2026-10-29T10:00:04.000Z"
category: "Research"
topics: ["llm"]
source_urls: ["https://divagr.com/blog/qwenputer","https://lobste.rs/s/zftely/qwenputer_fully_functioning"]
summary: "A fully functioning, deterministic RISC-V CPU called Qwenputer has been compiled into Qwen3.5 4B's weights using its Gated DeltaNet layers as RAM, running C and MicroPython inside forward passes for exact arithmetic."
---

# Qwenputer: a fully functioning, deterministic RISC\-V CPU inside Qwen3\.5

> [Open the canonical story](<https://aidr.today/871d1939?lang=en>)

**Published:** 2026-10-29T10:00:04.000Z
**Category:** Research
**Topics:** llm

## Summary

A fully functioning, deterministic RISC\-V CPU called Qwenputer has been compiled into Qwen3\.5 4B's weights using its Gated DeltaNet layers as RAM, running C and MicroPython inside forward passes for exact arithmetic\.

## Sources

- [Story source](<https://divagr.com/blog/qwenputer>)
- [Discussion](<https://lobste.rs/s/zftely/qwenputer_fully_functioning>)